SH7670 Datasheet, PDF (554/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
Bit Name
Initial
Value R/W Description
3
FECD00_DRE
0
R/W Destination Read Enable
0: Does not read the destination.
1: Reads the destination and updates the read
values.
2
FECD00_F2
0
R/W Descriptor Execution Flag 2
When 1, this bit explicitly indicates that this
descriptor is the last descriptor that should operate.
(Another method for explicitly indicating that this
descriptor is the last descriptor is to place an invalid
descriptor immediately after this descriptor.)
0: This descriptor is not the last descriptor that
should operate.
1: This descriptor is the last descriptor that should
operate.
1
FECD00_F1
0
R/W Descriptor Execution Flag 1
When this bit is 1, the FEC DMAC regards this
descriptor as the last descriptor in the descriptor ring
area and returns to the beginning (descriptor start
address) of the descriptor ring area when processing
of this descriptor ends.
0: This descriptor is not regarded as the last
descriptor in the descriptor ring area.
1: This descriptor is regarded as the last descriptor
in the descriptor ring area.
0
FECD00_F0
0
R/W Descriptor Execution Flag 0
When this bit is 0, processing of this descriptor ends
because this descriptor is invalid. If the descriptor
where FECD00_F0 is 0 is processed, the FEC
DMAC suspends FEC processing on the assumption
that FECC_E is 0.
When this bit is 1, this descriptor is valid. If this
descriptor is valid, the FEC DMAC sets this bit to 0
and writes back to the original address when
processing of this descriptor ends.
0: This descriptor is invalid.
1: This descriptor is valid.
Rev. 1.00 Nov. 14, 2007 Page 528 of 1262
REJ09B0437-0100