SH7670 Datasheet, PDF (680/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
17.3.8 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)
CFIFOSEL, D0FIFOSEL and D1FIFOSEL are registers that assign the pipe to the FIFO port, and
control access to the corresponding port.
The same pipe should not be specified by the CURPIPE bits in CFIFOSEL, D0FIFOSEL and
D1FIFOSEL. When the CURPIPE bits in D0FIFOSEL and D1FIFOSEL are cleared to B'000, no
pipe is selected.
The pipe number should not be changed while the DMA transfer is enabled.
These registers are initialized by a power-on reset.
(1) CFIFOSEL
Bit: 15 14 13
RCNT REW —
Initial value: 0
0
0
R/W: R/W R/W* R
12 11 10 9
8
7
—
MBW[1:0]
— BIGEND —
0
0
0
0
0
0
R R/W R/W R R/W R
6
5
4
3
2
1
0
— ISEL —
CURPIPE[3:0]
0
0
0
0
0
0
0
R R/W R R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15
RCNT
0
R/W Read Count Mode
Specifies the read mode for the value in the DTLN
bits in CFIFOCTR.
0: The DTLN bit is cleared when all of the receive
data has been read from the CFIFO.
(In double buffer mode, the DTLN bit value is
cleared when all the data has been read from a
single plane.)
1: The DTLN bit is decremented when the receive
data is read from the CFIFO.
Rev. 1.00 Nov. 14, 2007 Page 654 of 1262
REJ09B0437-0100