SH7670 Datasheet, PDF (911/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
2
WBSWP 0
R/W Byte Order for Access of HIFDATA
Specifies the byte order when an external device
accesses HIFDATA. See also section 20.8, Alignment
Control.
0: Aligned according to the BO bit.
1: Swapped in word units from the big endian order
and then swapped in byte units within each word.
The setting of the BO bit is ignored.
1
EDN
0
R/W Endian for HIFRAM Access
Specifies the byte order when HIFRAM is accessed by
the on-chip CPU.
0: Big endian (MSB first)
1: Little endian (LSB first)
0
BO
0
R/W Byte Order for Access of All HIF Registers Including
HIFDATA
Specifies the byte order when an external device
accesses all HIF registers including HIFDATA.
However, for the HIFDATA alignment, this bit is
referred to only when WBSWP = 0 and ignored when
WBSWP = 1. See also section 20.8, Alignment
Control.
0: Big endian (MSB first)
1: Little endian (LSB first)
Rev. 1.00 Nov. 14, 2007 Page 885 of 1262
REJ09B0437-0100