SH7670 Datasheet, PDF (827/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Figure 17.11 shows an example of buffer memory operation for this module.
CNTMD = 0
When packet is received
CNTMD = 1
When packet is received
Max Packet Size
Unused area
Interrupt issued
Max Packet Size
Max Packet Size
CNTMD = 0
When packet is sent
CNTMD = 1
When packet is sent
Interrupt issued
Max Packet Size
Max Packet Size
Unused area
Transmission
enabled
Max Packet Size
Transmission
enabled
Figure 17.11 Example of Buffer Memory Operation
(2) FIFO Port Functions
Table 17.24 shows the settings for the FIFO port functions of this module. In write access, writing
data until the buffer is full (or the maximum packet size for non-continuous transfers)
automatically enables sending of the data. To enable sending of data before the buffer is full (or
before the maximum packet size for non-continuous transfers), the BVAL bit in C/DnFIFOCTR
must be set to end the writing. Also, to send a zero-length packet, the BCLR bit in the same
register must be used to clear the buffer and then the BVAL bit set in order to end the writing.
In read access, reception of new packets is automatically enabled if all of the data has been read.
Data cannot be read when a zero-length packet is being received (DTLN = 0), so the BCLR bit in
the register must be used to release the buffer. The length of the data being received can be
confirmed using the DTLN bit in C/DnFIFOCTR.
Rev. 1.00 Nov. 14, 2007 Page 801 of 1262
REJ09B0437-0100