SH7670 Datasheet, PDF (566/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.5.2 Basic FEC Channel Operation
When "1" is written to the FECC_E bit of the FEC DMAC processing control register (FECC), the
FEC channel starts descriptor read. If the FECD00_F0 flag in the first longword is "1", descriptors
are fetched in turn to the appropriate register, starting from FECD00 in the first longword.
After descriptor read is completed, the FEC channel reads data from memory space indicated by a
source address and performs FEC operation (XOR calculation). After XOR calculation with all
source addresses is completed, the FEC channel writes back the result to destination address
space. After 1-descriptor processing ends, the FEC channel sets the FECD00_F0 flag to "0" and
writes back to the original area.
To support the FEC matrix operation of any number of rows and columns, the FEC channel
installed on the A-DMAC temporarily writes back the FEC operation result of source
rows/columns that can be processed by one descriptor to the destination address. If the FEC matrix
consists of two rows, the FEC matrix operation ends in one descriptor. If the FEC matrix consists
of 3 rows/columns or more, the FEC channel splits the matrix into several descriptors and
performs FEC matrix processing. If this processing must be split into several descriptors, use the
FECD00_DRE bit to control the FEC operation.
Figure 14.5 shows an example of descriptor configuration where the FEC matrix operation is split
into several descriptors for execution. In the first descriptor that starts the FEC operation,
FECD00_DRE is set to 0 because the operation result is not yet written. In the second and
subsequent descriptors, the FEC operation is continued. In other words, to XOR the calculation
result of the previous descriptor with the current descriptor source, FECD00_DRE is set to 1.
Piling up such descriptors till the number of rows or columns for the FEC matrix operation is met
makes it possible to obtain the last XOR operation result of the target row (column).
Any number of descriptors can be allocated onto memory in the ring form. Processing is started
from the descriptor allocated to the address indicated by the FEC DMAC processing descriptor
current address register (FECDCA). If descriptors where the FECD00_F0 flag of FEC DMAC
processing descriptor 0 (FECD00) is set to 1 continue, the FEC channel processes them one after
another. If the FECD00_F1 flag of FECD00 is 1, the FEC channel assumes that the end of
descriptor ring was detected and processes the descriptor allocated to the address indicated by the
FEC DMAC processing descriptor start address register (FECDSA). To end descriptor processing,
allocate the invalid descriptor where the FECD00_F0 flag of FECD00 is set to "0" or allocate the
last descriptor where the FECD00_F2 flag of FECD00 is set to "1".
Rev. 1.00 Nov. 14, 2007 Page 540 of 1262
REJ09B0437-0100