SH7670 Datasheet, PDF (950/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFO-
data-full interrupt, and receive-error interrupts are requested independently.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• In asynchronous mode, on-chip modem control functions (RTS and CTS).
• The quantity of data in the transmit and receive FIFO data registers and the number of receive
errors of the receive data in the receive FIFO data register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 22.1 shows a block diagram of the SCIF.
Module data bus
RxD
TxD
SCK
SCFRDR (16 stage)
SCRSR
SCFTDR (16 stage)
SCSMR
SCBRR
SCLSR
SCFDR
SCTSR
SCFCR
SCFSR
Baud rate
generator
SCSCR
SCSPTR
Transmission/reception
control
Parity generation
Clock
Parity check
External clock
CTS
RTS
SCIF
[Legend]
SCRSR: Receive shift register
SCFRDR: Receive FIFO data register
SCTSR: Transmit shift register
SCFTDR: Transmit FIFO data register
SCSMR: Serial mode register
SCSCR: Serial control register
SCFSR: Serial status register
SCBRR: Bit rate register
SCSPTR:Serial port register
SCFCR: FIFO control register
SCFDR: FIFO data count set register
SCLSR: Line status register
Figure 22.1 Block Diagram of SCIF
Peripheral
bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
BRI
Rev. 1.00 Nov. 14, 2007 Page 924 of 1262
REJ09B0437-0100