SH7670 Datasheet, PDF (345/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
8.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3)
The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that
specify the DMA transfer sources from peripheral modules in each channel. DMARS0 is for
channels 0 and 1, DMARS1 is for channels 2 and 3, DMARS2 is for channels 4 and 5, and
DMARS3 is for channels 6 and 7. Table 8.4 shows the specifiable combinations.
This register can specify transfer requests from six SCIF sources, two IIC3 sources, two CMT
sources, two USB sources, two SSI sources, and two SDHI sources.
• DMARS0
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH1 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH1 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH0 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH0 RID[1:0]
0
0
R/W R/W
• DMARS1
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH3 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH3 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH2 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH2 RID[1:0]
0
0
R/W R/W
• DMARS2
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH5 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH5 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH4 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH4 RID[1:0]
0
0
R/W R/W
• DMARS3
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH7 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH7 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH6 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH6 RID[1:0]
0
0
R/W R/W
Transfer requests from the various modules specify MID and RID as shown in table 8.4.
Rev. 1.00 Nov. 14, 2007 Page 319 of 1262
REJ09B0437-0100