SH7670 Datasheet, PDF (640/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 16 Serial Sound Interface (SSI)
16.4.4 Transmit Operation
Transmission can be controlled either by DMA or interrupt.
DMA control is preferred to reduce the processor load. In DMA control mode the processor will
only receive interrupts if there is an underflow or overflow of data or the DMAC has finished its
transfer.
The alternative method is using the interrupts that the SSI module generates to supply data as
required. This mode has a higher interrupt load as the module is only double buffered and will
require data to be written at least every system word period.
When disabling the module, the SSI clock* must remain present until the SSI module is in idle
state, indicated by the IIRQ bit.
Figure 16.20 shows the transmit operation in DMA control mode, and figure 16.21 shows the
transmit operation in interrupt control mode.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Input clock from the AUDIO_CLK pin when SCKD = 1.
Rev. 1.00 Nov. 14, 2007 Page 614 of 1262
REJ09B0437-0100