SH7670 Datasheet, PDF (586/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
Initial
Bit
Bit Name Value R/W Description
3
PWMDIV3 0
R/W These bits set the reference clock of the PWM control
2
PWMDIV2 0
R/W ^{output (PWMOUT) as a system clock (Bφ) division count.}
Set a division count between 1 and 1024. If a value outside
1
PWMDIV1 0
R/W _{the range is set, the operation of this LSI is not guaranteed.}
0
PWMDIV0 0
R/W _{This setting should be modified only when the PIDEN bit is}
0.
0000: 1
1000: 256
0001: 2
1001: 512
0010: 4
1010: 1024
0011: 8
1011: 2048 (invalid)
0100: 16
1100: 4096 (invalid)
0101: 32
1101: 8192 (invalid)
0110: 64
1110: 16384 (invalid)
0111: 128
1111: 32768 (invalid)
Rev. 1.00 Nov. 14, 2007 Page 560 of 1262
REJ09B0437-0100