SH7670 Datasheet, PDF (1282/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Connection to PHY-LSI ......................... 435
Control Signal Timing .......................... 1186
CPU .......................................................... 29
Crystal oscillator..................................... 345
CSn assert period expansion................... 231
Cycle steal mode..................................... 334
D
Data array ......................................... 88, 103
Data array read ....................................... 103
Data array write ...................................... 103
Data format in registers ............................ 34
Data formats in memory ........................... 34
Data register.......................................... 1039
Data transfer instructions.......................... 55
Data transfer with
interrupt request signals.......................... 166
DC Characteristics................................ 1173
Deep power-down mode......................... 271
Delayed branch instructions ..................... 37
Denormalized numbers............................. 80
Direct memory access controller
(DMAC) ................................................. 293
Displacement accessing............................ 39
Divider 1................................................. 345
Divider 2................................................. 345
DMA transfer flowchart ......................... 322
DMAC Module Timing ........................ 1216
DMAC That Works with
Encryption/Decryption and Forward
Error Correction Core (A-DMAC) ......... 493
DREQ pin sampling timing .................... 339
Dual address mode.................................. 331
E
Effective address calculation .................... 40
Electrical Characteristics ...................... 1171
Endian..................................................... 217
Rev. 1.00 Nov. 14, 2007 Page 1256 of 1262
REJ09B0437-0100
Equation for getting SCBRR value......... 945
EtherC Module Signal Timing.............. 1233
EtherC receiver ....................................... 427
EtherC transmitter................................... 425
Ethernet controller (EtherC) ................... 395
Ethernet controller direct memory
access controller (E-DMAC) .................. 437
Exception handling ................................. 107
Exception handling state ........................... 73
Exception handling vector table.............. 111
Exception source generation immediately
after delayed branch instruction.............. 127
Exceptions triggered by instructions....... 123
External request mode............................. 323
F
Fixed mode ............................................. 327
Floating-point exceptions.......................... 85
Floating-point format ................................ 76
Floating-point operation instruction........ 126
Floating-point operation instructions ........ 67
Floating-point ranges ................................ 78
Floating-point registers ............................. 81
Floating-point unit (FPU) ......................... 75
Flow control............................................ 434
Format of double-precision
floating-point number ............................... 76
Format of single-precision
foating-point number ................................ 76
FPU exception handling............................ 86
FPU exception sources.............................. 85
FPU-related CPU instructions................... 69
G
General illegal instructions ..................... 124
General registers ....................................... 29
Global base register (GBR)....................... 31