SH7670 Datasheet, PDF (315/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
Figure 7.43 shows sample estimation of idle cycles between access cycles. In the actual operation,
the idle cycles may become shorter than the estimated value due to the write buffer effect or may
become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU
instruction execution or CPU register conflicts. Please consider these errors when estimating the
idle cycles.
Sample estimation of the number of idle clock cycles (states) between cycles of bus access
We consider CPU access for the transfer of data from the CS5 to the CS6 space.
For this transfer, the sequence read from CS5 →read from CS5 →write to CS6→write to CS6 ... is repeated.
• Condition
0 is specified as the number of idle cycles between CS5BCR and CS6BCR.
WM bit in CS5WCR and CS6WCR = 1 (external WAIT_ pin disabled)
HW[1:0] = 00 (no delay of CS negation)
If:Bf= 4:1
No other processing proceeds during the transfer.
CS5 and CS6 are connected to SRAM for access in 32-bit units by a 32-bit-wide bus.
The items that decide the number of idle cycles are estimated for the different transitions on between bus cycles.
R indicates reading and W indicates writing in the table below.
Item
R→R R→W W→W W→R
Note
(1)/(2)
0
0
0
0 Since CSnBCR is set to 0
(3)/(4)
0
0
0
0 When the WM bit is set to 1
(5)
1
1
0
0 Generated after the read cycle
(6)
0
2
2
0 See the description for If:Bf= 4:1 in table 7.21.
(7)
(5)+(6)+(7)
0
1
0
0
The effect of the write buffer is that idle cycles are not
generated the second time.
1
4
2
0
(8)
0
0
0
0
Due to SRAM→SRAM
Estimated number
of idle cycles
1
4
2
0 Maximum value among (1)/(2), (3)/(4), (5)+(6)+(7), and (8)
The mismatch in the case of W→R is because the estimate
Actual number
of idle cycles
1
4
2
1
of the number of idle cycles for item (6) was zero. Since a
loop-decision instruction is actually executed here,
an idle cycle is generated internally.
Figure 7.43 Comparison between Estimated Idle Cycles and Actual Value
Rev. 1.00 Nov. 14, 2007 Page 289 of 1262
REJ09B0437-0100