SH7670 Datasheet, PDF (561/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.4 Channel Operation
14.4.1 Descriptor Format
The A-DMAC can automatically perform DMA transfer between memory and the STIF without
the CPU based on the descriptor containing information such as a buffer pointer and its data size.
The A-DMAC automatically performs operations such as reading data from memory and writing
the decrypted data to the STIF according to the information stored in this descriptor.
Figure 14.2 shows the descriptor format. The gray parts in the figure are ignored when descriptor
processing is started and "0" is written back to these parts after descriptor processing ends. For
details on each bit, see section 14.2.6, Channel [i] Processing Descriptor 0 Register (C[i]D0)
[Control] (i = 0, 1), to section 14.2.10, Channel [i] Processing Descriptor 4 Register (C[i]D4)
[Checksum Value Write Address] (i = 0, 1).
Bit
Address
0
31 30 29 28
CRDO[3:0]
27-26 25-24
CHDO[3:0]
23-20 19 18 17-16
SO[3:0] DA SA CSM[1:0]
+4
D1 [31:0]
+8
D2 [31:0]
+12
DWE DIE
+16
D4 [31:1]
+20
+24
+28
Figure 14.2 Descriptor Format
15-3
D3 [15:0]
2-1 0
F[2:0]
A descriptor is 16/32-byte variable length or 32-byte fixed length. Select variable length or fixed
length from the variable-length descriptor control flag (C[i]C_VLD) of the channel [i] processing
control register (C[i]C). If C[i]C_VLD is set to 1 to operate the descriptor as the variable-length
descriptor, the remaining 16 bytes are read when the following conditions are met:
• Checksum calculation result write-back is set (C[i]CSM0 = 1).
Rev. 1.00 Nov. 14, 2007 Page 535 of 1262
REJ09B0437-0100