SH7670 Datasheet, PDF (126/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 4 Cache
Operations in sections 4.3.2 to 4.3.5 are compiled in table 4.8.
Table 4.8 Cache Operations
Cache
Hit/ Write-back mode/
CPU Cycle miss write through mode
U Bit
External Memory
Accession
(through internal bus)
Cache Contents
Instructio Instruction Hit 
n cache fetch

Not generated
Not renewed
Miss 

Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
Operand Prefetch/ Hit Either mode is
cache read
available
x
Not generated
Not renewed
Miss Write-through mode 
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
Write-back mode
0
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
1
Cache renewal cycle is
Renewed to new values by
generated. Succeedingly
cache renewal cycle
write-back cycle in write-back
buffer is generated.
Write
Hit Write-through mode 
Write cycle CPU issues is
generated.
Renewed to new values by write
cycle the CPU issues
Write-back mode
x
Not generated
Renewed to new values by write
cycle the CPU issues
Miss Write-through mode 
Write cycle CPU issues is
generated.
Not renewed*
Write-back mode
0
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle.
Subsequently renewed again to
new values in write cycle CPU
issues.
1
Cache renewal cycle is
Renewed to new values by
generated. Succeedingly
cache renewal cycle.
write-back cycle in write-back Subsequently renewed again to
buffer is generated.
new values in write cycle CPU
issues.
[Legend]
x: Don't care.
Note: Cache renewal cycle: 16-byte read access, write-back cycle in write-back buffer: 16-byte
write access
* Neither LRU renewed. LRU is renewed in all other cases.
Rev. 1.00 Nov. 14, 2007 Page 100 of 1262
REJ09B0437-0100