SH7670 Datasheet, PDF (919/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.10 HIFDREQ Trigger Register (HIFDTR)
HIFDTR is a 32-bit register. Writing to HIFDTR by the on-chip CPU asserts the HIFDREQ pin.
HIFDTR cannot be accessed by an external device.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0










-



 DTRG
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Initial
Bit
Bit Name Value R/W
31 to 1 
All 0
R
0
DTRG
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
HIFDREQ Trigger
When 1 is written to this bit, the HIFDREQ pin is
asserted according to the setting of the DMD and
DPOL bits in HIFSCR. This bit is automatically cleared
to 0 in synchronization with negate of the HIFDREQ
pin.
Though this bit can be set to 1 by the on-chip CPU, it
cannot be cleared to 0.
To avoid conflict between clearing of this bit by negate
of the HIFDREQ pin and setting of this bit by the on-
chip CPU, make sure this bit is cleared to 0 before
setting this bit to 1 by the on-chip CPU.
Writing 0 is invalid.
Rev. 1.00 Nov. 14, 2007 Page 893 of 1262
REJ09B0437-0100