SH7670 Datasheet, PDF (559/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Mode Name
CTR
(Counter Mode)
Description
Mode in which to encrypt "counter" consisting of random numbers and
counters and XOR the obtained block with plain text (ciphertext) to
generate ciphertext (plain text).
The counter is incremented per processing block. This mode supports
parallel processing.
If the AES encryption/decryption function is used by the DMAC channel, the A-DMAC uses the
descriptors to update keys and initial vectors. The A-DMAC can also use the descriptors to output
the intermediate values (intermediate result) of the initial vectors obtained when
encryption/decryption was performed in encryption operating mode other than ECB.
14.3.2 Checksum
Checksum is a data error detection scheme. Checksum splits the entered data in 16-bit units and
calculates their 1's complement sum to detect an error. For example, TCP checksum used to detect
packet errors on the receiving side splits information called an IP pseudo header, TCP header, and
TCP payload data in 16-bit units and calculates their 1's complement sum. If the obtained 1's
complement sum is H'FFFF or H'0000, it indicates that no packet error occurred. If the 1's
complement sum is not H'FFFF and H'0000, it indicates that a packet error occurred.
The A-DMAC has a function to calculate the 1's complement sum of data obtained via DMA
transfer.
14.3.3 FEC Channel
The A-DMAC has one channel for FEC operation. This channel can perform XOR operation for
the data obtained via DMA transfer and write back to memory because it is of a descriptor
structure that can cope with FEC operation of any number of rows.
Rev. 1.00 Nov. 14, 2007 Page 533 of 1262
REJ09B0437-0100