SH7670 Datasheet, PDF (592/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
15.3.12 STIFSTC0, STIFSTC1 Registers (STSTC0R, STSTC1R)
STSTC0R and STSTC1R are 32-bit registers that interface with the internal STC register.
STPCR0R and STPCR1R are initialized to H'00000000 by a power-on reset. These registers
compose a 42-bit register including STC base (33 bits) and STC extension (9 bits). The PCR base
and PCR extension are stored in STCB32 to STCB0 and STCX8 to STCX0 respectively. Reading
or writing this 42-bit register does not cause the read/write result to be reflected directly in clock
recovery.
• STSTC0R
Initial
Bit
Bit Name Value R/W
31 to 10 
All 0 R
9 to 0 STCB32 to All 0 R/W
STCB23
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
STC Base
• STSTC1R
Initial
Bit
Bit Name Value R/W Description
31 to 9 STCB22 to All 0 R/W STC Base
STCB0
8 to 0 STCX8 to All 0 R/W STC Extension
STCX0
Note:
If PCR_PID arrives during data read, the read value is overwritten and becomes undefined.
Therefore, confirm that there is no PCR_PID during data read with the PCRF bit in STSTR.
Specifically, set the PCRF bit to 0 and then start reading the receive data. Whenever PCRF
is 1, take this procedure.
Rev. 1.00 Nov. 14, 2007 Page 566 of 1262
REJ09B0437-0100