SH7670 Datasheet, PDF (481/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name value R/W Description
1
PRECE
0
R/W PRE Bit Copy Directive
0: Indicates the PRF bit state in bit RFS1 of the receive
descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit RFS1 of the receive descriptor
0
CERFCE 0
R/W CERF Bit Copy Directive
0: Indicates the CERF bit state in bit RFS0 of the
receive descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit RFS0 of the receive descriptor
13.2.9 Receive Missed-Frame Counter Register (RMFCR)
RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not
transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive
frames in the FIFO are discarded. The number of frames discarded at this time is counted. When
the value in this register reaches H'FFFF, counting-up is halted. When this register is read, the
counter value is cleared to 0. Write operations to this register have no effect.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MFC[15:0]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
31 to 16 
Initial
value
All 0
15 to 0 MFC[15:0] All 0
R/W
R
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Missed-Frame Counter
Indicate the number of frames that are discarded and
not transferred to the receive buffer during reception.
Rev. 1.00 Nov. 14, 2007 Page 455 of 1262
REJ09B0437-0100