SH7670 Datasheet, PDF (490/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.19 Receive Data Padding Setting Register (RPADIR)
RPADIR is a 32-bit readable/writable register that performs the padding of receive data. Before
setting this register again, reset the software with the SWR bit in the E-DMAC mode register
(EDMR).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16













 PADS1 PADS0
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0










PADR[5:0]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 18 
Initial
value
All 0
R/W

17
PADS1
0
R/W
16
PADS0
0
R/W
15 to 6 
All 0

5 to 0 PADR[5:0] 000000 R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Padding size
00: No padding
01: Padding of one byte
10: Padding of two bytes
11: Padding of three bytes
Reserved
These bits are always read as 0. The write value
should always be 0.
Padding Range
H'00: Data equivalent to the padding size is inserted in
the first byte.
H'01: Data equivalent to the padding size is inserted in
the second byte.
:
:
H'3E: Data equivalent to the padding size is inserted in
the 63rd byte.
H'3F: Data equivalent to the padding size is inserted in
the 64th byte.
Rev. 1.00 Nov. 14, 2007 Page 464 of 1262
REJ09B0437-0100