SH7670 Datasheet, PDF (382/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 9 Clock Pulse Generator (CPG)
Bit
4
3
2 to 0
Bit Name
IFC
Initial
Value
0

0
PFC[2:0] 011
R/W Description
R/W Internal Clock Frequency Division Ratio
This bit specifies the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit.
0: × 1 time
1: × 1/2 time
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Peripheral Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit.
000: Reserved (setting prohibited)
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
110: × 1/12 time
111: Reserved (setting prohibited)
Rev. 1.00 Nov. 14, 2007 Page 356 of 1262
REJ09B0437-0100