SH7670 Datasheet, PDF (467/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.2 E-DMAC Transmit Request Register (EDTRR)
The EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC.
When transmission of one frame is completed, the next descriptor is read. If the transmit
descriptor active bit in this descriptor has the "active" setting, transmission is continued. If the
transmit descriptor active bit has the "inactive" setting, the TR bit is cleared and operation of the
transmit DMAC is halted.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: _{15 14 13 12 11 10}
9
8
7
6
5
4
3
2
1
0















TR
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: _R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Initial
Bit
Bit Name value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
TR
0
R/W Transmit Request
0: Transmission-halted state. Writing 0 does not stop
transmission. Termination of transmission is
controlled by the active bit in the transmit descriptor
1: Start of transmission. The relevant descriptor is
read and a frame is sent with the transmit active bit
set to 1
Rev. 1.00 Nov. 14, 2007 Page 441 of 1262
REJ09B0437-0100