SH7670 Datasheet, PDF (546/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Initial
Bit
Bit Name
Value R/W Description
0
FECC_E
0
R/W Execution Request
Setting this bit to 1 causes FEC processing to be
started. Setting this bit to 0 during FEC processing
causes FEC processing to be suspended. After FEC
processing ends, this bit is automatically set to 0.
There are two methods for understanding the FEC
DMAC operating state. In one, when the FEC DMAC
is executed, FECC_EIE is set to 1 to accept the
"operation end" interrupt request. In the other, the
operating state is observed till the key of this bit is
set to 0.
0: FEC processing is halted.
1: FEC processing is in progress.
14.2.12 FEC DMAC Processing Interrupt Request Register (FECI)
ad_irqfec_n is asserted as negation of logical OR of all bits in this register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0



FECI_
DI



FECI_
LI



FECI_
NI



FECI_
EI
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R
R
R R/W R
R
R R/W R
R
R R/W
Rev. 1.00 Nov. 14, 2007 Page 520 of 1262
REJ09B0437-0100