SH7670 Datasheet, PDF (220/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
Bit
5 to 2
1, 0
Bit Name

Initial
Value
All 0
HW[1:0] 00
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Delay Cycles from RD, WEn Negation to Address,
CS5 Negation
Specify the number of delay cycles from RD and WEn
negation to address and CS5 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS6WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
BAS
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Bit
31 to 21
Bit Name

Initial
Value
All 0
20
BAS
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W SRAM with Byte Selection Byte Access Select
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RD/WR signal at the write
timing.
Rev. 1.00 Nov. 14, 2007 Page 194 of 1262
REJ09B0437-0100