SH7670 Datasheet, PDF (358/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
CKIO
A25 to A0
CSn
Transfer source
address
Transfer destination
address
D31 to D0
RD
WEn
DACKn
(Active-low)
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 8.6 Example of DMA Transfer Timing in Dual Mode
(Transfer Source: Normal Memory, Transfer Destination: Normal Memory)
Rev. 1.00 Nov. 14, 2007 Page 332 of 1262
REJ09B0437-0100