SH7670 Datasheet, PDF (166/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 6 Interrupt Controller (INTC)
Bit
Bit Name
7
IRQ7F
6
IRQ6F
5
IRQ5F
4
IRQ4F
3
IRQ3F
2
IRQ2F
1
IRQ1F
0
IRQ0F
[Legend]
n = 7 to 0
Initial
Value
0
0
0
0
0
0
0
0
R/W Description
R/(W)* ^{IRQ Interrupt Request}
R/(W)* ^{These bits indicate the status of the IRQ7 to IRQ0}
interrupt requests.
R/(W)* _{Level detection:}
R/(W)* _{0: IRQn interrupt request has not occurred}
R/(W)* [Clearing condition]
R/(W)* • IRQn input is high
R/(W)* ^{1: IRQn interrupt has occurred}
R/(W)* ^{[Setting condition]}
• IRQn input is low
Edge detection:
0: IRQn interrupt request is not detected
[Clearing conditions]
• Cleared by reading IRQnF while IRQnF = 1, then
writing 0 to IRQnF
• Cleared by executing IRQn interrupt exception
handling
1: IRQn interrupt request is detected
[Setting condition]
• Edge corresponding to IRQn1S or IRQn0S of
ICR1 has occurred at IRQn pin
Rev. 1.00 Nov. 14, 2007 Page 140 of 1262
REJ09B0437-0100