SH7670 Datasheet, PDF (555/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.2.16 FEC DMAC Processing Descriptor 1 Register (FECD01D0A) [Destination
Address]
Do not write any value to this register when FECC_E is set to 1.
Bit: 31
Initial Value: 0
R/W: R/W
30
0
R/W
29
0
R/W
28
0
R/W
27
0
R/W
26
0
R/W
25 24 23 22
FECD01D0A[31:16]
0
0
0
0
R/W R/W R/W R/W
21
0
R/W
20
0
R/W
19
0
R/W
18
0
R/W
17
0
R/W
16
0
R/W
Bit: 15
Initial Value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
8
7
6
FECD01D0A[15:0]
0
0
0
0
R/W R/W R/W R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
31 to 0
Bit Name
Initial
Value R/W Description
FECD01D0A[31:0] All 0 R/W Destination Address
Specify a processing data write-back destination
address.
14.2.17 FEC DMAC Processing Descriptor 2 Register (FECD02S0A) [Source 0 Address]
Do not write any value to this register when FECC_E is set to 1.
Bit: 31
Initial Value: 0
R/W: R/W
30
0
R/W
29
0
R/W
28
0
R/W
27
0
R/W
26
0
R/W
25 24 23 22
FECD02S0A[31:16]
0
0
0
0
R/W R/W R/W R/W
21
0
R/W
20
0
R/W
19
0
R/W
18
0
R/W
17
0
R/W
16
0
R/W
Bit: 15
Initial Value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
8
7
6
FECD02S0A[15:0]
0
0
0
0
R/W R/W R/W R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
31 to 0
Bit Name
Initial
Value R/W Description
FECD02S0A[31:0] All 0 R/W Specify the start address of source 0 data.
Rev. 1.00 Nov. 14, 2007 Page 529 of 1262
REJ09B0437-0100