SH7670 Datasheet, PDF (453/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
3. The transmitter sends the SFD, data, and CRC sequentially. At the end of transmission, the
transmit E-DMAC generates a transmission complete interrupt (TC). If a collision or the
carrier-not-detected state occurs during data transmission, these are reported as interrupt
sources.
4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is
more transmit data, continues transmitting.
12.4.2 Reception
The EtherC receiver separates the frame data (MII into preamble, SFD, DA (destination address),
SA (Source address), type/length, Data, and CRC data) and outputs DA, SA, type/length, Data to
the E-DMAC. Figure 12.3 shows the state transitions of the EtherC receiver.
Illegal carrier
detection
RX-DV negation
Idle
RE set
Reception
halted
RE reset
Reset
Start of frame
Preamble ^reception
detection
Wait for SFD
reception
SFD
reception
Destination address
Promiscuous and other
reception
station destination address
Own destination address
or broadcast
or multicast
Receive error
or promiscuous
Error
detection
Data
Error
detection
reception
notification*
Receive error
detection
End of
reception
Normal reception
[Legend]
SFD: Start frame delimiter
Note: * The error frame also transmits data to the buffer.
CRC
reception
Figure 12.3 EtherC Receiver State Transmissions
Rev. 1.00 Nov. 14, 2007 Page 427 of 1262
REJ09B0437-0100