SH7670 Datasheet, PDF (1243/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
29.4.6 SCIF Module Timing
Table 29.11 SCIF Module Timing
Conditions:
V_CC = V_CC (PLL) = DV12 = UV12 = 1.1 to 1.3 V, V_CCQ = DV33 = 3.1 to 3.5 V,
AV12 = 1.1 to 1.3 V, AV33 = 3.1 to 3.5 V,
V_SS = V_SS (PLL) = DG12 = UG12 = V_SSQ = DG33 = AG12 = AG33 = 0 V,
Ta = –20 to 70°C (regular specifications),
–40 to 85°C (wide temperature specifications)
Item
Symbol Min.
Max.
Unit
Input clock cycle Clocked synchronous tScyc
12

tpcyc
Asynchronous
4

tpcyc
Input clock rise time
tSCKr

1.5
tpcyc
Input clock fall time
tSCKf

1.5
tpcyc
Input clock width
tSCKW
0.4
0.6
tScyc
Transmit data delay time
(Clocked synchronous)
tTXD

3 × tpcyc +15 tpcyc
Receive data setup time
(Clocked synchronous)
tRXS
4 × tpcyc +15 
ns
Receive data hold time
(Clocked synchronous)
tRXH
100

ns
Note: t_pcyc indicates the peripheral clock (Pφ) cycle.
Figure
29.40
29.40
29.40
29.40
29.40
29.41
29.41
29.41
SCK
t_SCKW
t_SCKr
t_Scyc
t_SCKf
Figure 29.40 SCK Input Clock Timing
Rev. 1.00 Nov. 14, 2007 Page 1217 of 1262
REJ09B0437-0100