SH7670 Datasheet, PDF (203/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
7.4.1 Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0







DMAIW[2:0]
DMA
IWA



HIZ HIZ
MEM CNT
Initial Value: 0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R/W R/W R/W R
R
R R/W R/W
Bit
Bit Name
31 to 13 
Initial
Value
All 0
12

1
11 to 9 
All 0
8 to 6 DMAIW[2:0] 000
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Reserved
This bit is always read as 1. The write value should
always be 1.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Wait states between access cycles when DMA single
address transfer is performed.
Specify the number of idle cycles to be inserted after
an access to an external device with DACK when DMA
single address transfer is performed. The method of
inserting idle cycles depends on the contents of
DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Rev. 1.00 Nov. 14, 2007 Page 177 of 1262
REJ09B0437-0100