SH7670 Datasheet, PDF (823/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
(b) FIFO Buffer Clearing
Table 17.21 shows the clearing of the FIFO buffer memory by this module. The buffer memory
can be cleared using the three bits indicated below.
Table 17.21 List of Buffer Clearing Methods
Bit Name
Register
Function
Clearing
method
BCLR
CFIFOCTR
DnFIFOCTR
Clears the buffer memory
on the CPU side
Cleared by writing 1
DCLRM
DnFIFOSEL
ACLRM
PIPEnCTR
In this mode, after the data This is the auto buffer clear
of the specified pipe has mode, in which all of the
been read, the buffer
received packets are
memory is cleared
discarded.
automatically.
1: Mode valid
1: Mode valid
0: Mode invalid
0: Mode invalid
(c) Buffer Areas
Table 17.22 shows the FIFO buffer memory map of this controller. The buffer memory has special
fixed areas to which pipes are assigned in advance, and user areas that can be set by the user.
The buffer for the DCP is a special fixed area that is used both for control read transfers and
control write transfers.
The PIPE6 to PIPE9 area is assigned in advance, but the area for pipes that are not being used can
be assigned to PIPE1 to PIPE5 as a user area.
The settings should ensure that the various pipes do not overlap. Note that each area is twice as
large as the setting value in the double buffer.
Also, the buffer size should not be specified using a value that is less than the maximum packet
size.
Rev. 1.00 Nov. 14, 2007 Page 797 of 1262
REJ09B0437-0100