SH7670 Datasheet, PDF (541/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
31, 30
Bit Name
—
29
C[i]DWE
28
C[i]DIE
27 to 16 —
Initial
Value R/W
All 0 R/W
0
R/W
0
R/W
All 0 R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
"1 Descriptor Processing End" Interrupt Release
Wait Enable
If this bit is 1 and the "1 descriptor processing"
interrupt is requested, the A-DMAC waits for the
interrupt release before it moves to next descriptor
processing.
0: Does not observe the "1 descriptor processing
end" interrupt.
1: Enables "1 descriptor processing end" interrupt
release wait.
"1 Descriptor Processing End" Interrupt Request
Enable
Specifies whether to enable or disable the "1
descriptor processing end" interrupt when
processing of this descriptor ends. Processing does
not end even if the "1 descriptor processing end"
interrupt request is enabled.
0: Disables the "1 descriptor processing end"
interrupt request.
1: Enables the "1 descriptor processing end"
interrupt request.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 14, 2007 Page 515 of 1262
REJ09B0437-0100