SH7670 Datasheet, PDF (909/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.3 HIF Status/Control Register (HIFSCR)
HIFSCR is a 32-bit register used to control the HIFRAM access mode and endian setting.
HIFSCR can be read from and written to by the on-chip CPU. Access to HIFSCR by an external
device should be performed with HIFSCR specified by bits REG5 to REG0 in HIFIDX and the
HIFRS pin low.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7



 DMD DPOL BMD BSEL 
Initial Value: 0
0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R
6
5
4
 MD1 
1 0/1 0
R
R
R
3
2
1
0
 WBSWP EDN BO
0
0
0
0
R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 12 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11
DMD
0
R/W DREQ Mode
10
DPOL
0
R/W DREQ Polarity
Controls the assert mode for the HIFDREQ pin. For
details on the negate timing, see section 20.7, External
DMAC Interface.
00: For a DMAC transfer request to an external device,
low level is generated at the HIFDREQ pin. The
default for the HIFDREQ pin is high-level output.
01: For a DMAC transfer request to an external device,
high level is generated at the HIFDREQ pin. The
default for the HIFDREQ pin is low-level output.
10: For a DMAC transfer request to an external device,
falling edge is generated at the HIFDREQ pin. The
default for the HIFDREQ pin is high-level output.
11: For a DMAC transfer request to an external device,
rising edge is generated at the HIFDREQ pin. The
default for the HIFDREQ pin is low-level output.
Rev. 1.00 Nov. 14, 2007 Page 883 of 1262
REJ09B0437-0100