SH7670 Datasheet, PDF (410/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 11 Power-Down Modes
11.2.5 System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM
(high-speed). SYSCR1 is valid only in byte access.
When an RAME bit is set to 1, the corresponding on-chip RAM (high-speed) area is enabled.
When an RAME bit is cleared to 0, the corresponding on-chip RAM (high-speed) area cannot be
accessed. In this case, an undefined value is returned when reading data or fetching an instruction
from the on-chip RAM (high-speed), and writing to the on-chip RAM (high-speed) is ignored. The
initial value of an RAME bit is 1.
Note that when clearing the RAME bit to 0 to disable the on-chip RAM (high-speed), be sure to
execute an instruction to read from or write to the same arbitrary address in each page before
setting the RAME bit. If such an instruction is not executed, the data last written may not be
written to the on-chip RAM (high-speed). Furthermore, an instruction to access the on-chip RAM
(high-speed) should not be located immediately after the instruction to write to SYSCR1. If an on-
chip RAM (high-speed) access instruction is set, normal access is not guaranteed.
If this bit is set to 1 to enable the on-chip RAM (high-speed), the SYSCR1 read instruction must
be placed immediately after the SYSCR1 write instruction. If the on-chip RAM (high-speed)
access instruction is placed immediately after the SYSCR1 write instruction, then normal access
will not be guaranteed.
Note: See section 11.4, Usage Notes, when writing data to this register.
Bit: 7
6
5
4
3
2
1
0



 RAME3 RAME2 RAME1 RAME0
1
1
1
1
1
1
1
1
R/W: R
R
R
R R/W R/W R/W R/W
Bit
7 to 4
3
Bit Name

Initial
Value
All 1
RAME3
1
R/W Description
R
Reserved
These bits are always read as 1. The write value
should always be 1.
R/W RAM Enable 3 (corresponding RAM addresses: Page
3 in on-chip RAM (high-speed)*)
0: On-chip RAM (high-speed) disabled
1: On-chip RAM (high-speed) enabled
Rev. 1.00 Nov. 14, 2007 Page 384 of 1262
REJ09B0437-0100