SH7670 Datasheet, PDF (897/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

(a) Under normal conditions
Synchronization
clock*1
SCL pin
Internal SCL monitor
V_IH
Internal delay*²
Section 19 I²C Bus Interface 3 (IIC3)
The monitor value is at a high level.
SCL monitor time
(b) When the slave device is first driven to a low level
Synchronization
clock*¹
SCL pin
Internal SCL monitor
Low-level output
from the slave
V_IH
Internal
delay*²
SCL does not produce a low-level output.
V_IH
Internal delay*²
The monitor value is
at a low level.
The monitor value is
at a high level.
The monitor value is
at a high level.
SCL monitor time
SCL monitor time
SCL monitor time
(c) When rising of SCL is gradual
Synchronization
clock*1
SCL pin
V_IH
SCL does not produce a low-level output.
Internal SCL monitor
Internal
delay*²
The monitor value is at a low level.
SCL monitor time
Notes: 1.
2.
Clock of the transfer rate set by the CKS3 to CKS0 bits in I2C bus control register 1 (ICCR1)
The value is 3 to 4 tpcyc when the NF2CYC bit in the NF2CYC register (NF2CYC) is 0;
the value is 4 to 5 tpcyc when the NF2CYC bit is 1.
Figure 19.22 Bit Synchronous Circuit Timing
This is different
from the set frequency.
Rev. 1.00 Nov. 14, 2007 Page 871 of 1262
REJ09B0437-0100