SH7670 Datasheet, PDF (584/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
15.3.8 STIFPWM Mode Register (STPWMMR)
STPWMMR is a 32-bit register that selects PWM mode, sets PWM control cycle, reference bit
shift amount, and reference clock, enables/disables PID filtering, and sets the PID of a PCR packet
to be filtered. STPWMMR is initialized to H'00000000 by a power-on reset.
Bit
31 to 29
Bit Name

Initial
Value
All 0
28 to 16 PID12 to All 0
PID0
15
PIDEN 0
14
PWMUEN 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W These bits set the PID (PCR_PID) of filtering target PCR
packet.
R/W Enables or disables PCR packet filtering.
0: Filtering is disabled.
1: Filtering is enabled.
R/W Selects whether to reflect the PWM control difference
(internal STC - internal PCR) in the PWM control output
according to the comparison of the residual upper bits
(comparison target bits) in the comparison of bits 0 to 11.
The comparison result of target bits is reflected in UNZF.
This bit is valid only when PWMSEL is 0.
0: When the comparison results in a mismatch, PWM
control variable is reflected in PWM control.
[Match: UNZF = 0] PWM control variable is reflected in
PWM output control.
[Mismatch: UNZF = 1] PWM control variable is reflected in
PWM output control.
1: When the comparison results in a mismatch, PWM
control variable is not reflected in PWM control.
[Match: UNZF = 0] PWM control variable is reflected in
PWM output control.
[Mismatch: UNZF = 1] PWM control variable is not reflected
in PWM output control.
Rev. 1.00 Nov. 14, 2007 Page 558 of 1262
REJ09B0437-0100