SH7670 Datasheet, PDF (978/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
22.3.9 FIFO Control Register (SCFCR)
SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU. It is initialized to H'0000 by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
RSTRG[2:0]
RTRG[1:0]
TTRG[1:0]
MCE TFRST RFRST LOOP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 11 —
Initial
Value
All 0
10 to 8 RSTRG[2:0] 000
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W RTS Output Active Trigger
When the quantity of receive data in receive FIFO data
register (SCFRDR) becomes more than the number
shown below, RTS signal is set to high.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
Rev. 1.00 Nov. 14, 2007 Page 952 of 1262
REJ09B0437-0100