SH7670 Datasheet, PDF (730/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
11 to 7 
6 to 0 MXPS[6:0]
Initial
Value R/W Description
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
H'40
R/W Maximum Packet Size
Specifies the maximum data payload (maximum
packet size) for the DCP.
These bits are initialized to H'40 (64 bytes).
These bits should be set to the value based on the
USB Specification.
These bits should be set while CSSTS is 0 and PID
is NAK and before the pipe is selected by the
CURPIPE bits.
Before modifying these bits after modifying the PID
bits for the corresponding pipe from BUF to NAK,
check that CSSTS and PBUSY are 0. However, if
the PID bits have been modified to NAK by this
module, checking PBUSY through software is not
necessary.
While MXPS is 0, do not write to the FIFO buffer or
do not set PID to BUF.
17.3.30 DCP Control Register (DCPCTR)
DCPCTR is a register that is used to confirm the buffer memory status, change and confirm the
data PID sequence bit, and set the response PID for the DCP.
This register is initialized by a power-on reset. The CCPL and PID[1:0] bits are initialized by a
USB bus reset.
Bit: 15 14 13 12 11 10
BSTS
SUREQ
CSCLR
CSCTS
SUREQ
CLR
—
Initial value: 0
0
0
0
0
0
R/W: R R/W*² R/W*¹ R/W R/W*¹ R
9
8
7
6
5
4
3
2
1
0
— SQCLR SQSET SQMON PBUSY PINGE — CCPL
PID[1:0]
0
0
0
1
R R/W*¹ R/W*¹ R
0
0
0
0
0
0
R R/W R R/W*¹ R/W R/W
Rev. 1.00 Nov. 14, 2007 Page 704 of 1262
REJ09B0437-0100