SH7670 Datasheet, PDF (312/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
No. Condition
Description
Range Note
[5] Read data
transfer cycle
One idle cycle is inserted after a 0 or 1
read access is completed. This idle
cycle is not generated for the first or
middle cycles in divided access
cycles. This is neither generated
when the HM[1:0] bits in CSnWCR
are not B'00.
One idle cycle is always
generated after a read cycle
with SDRAM or PCMCIA
interface.
[6] Internal bus External bus access requests from 0 or
idle cycles, etc. the CPU or DMAC and their results larger
are passed through the internal
bus. The external bus enters idle
state during internal bus idle cycles
or while a bus other than the
external bus is being accessed.
This condition is not effective for
divided access cycles, which are
generated by the BSC when the
access size is larger than the
external data bus width.
The number of internal bus
idle cycles may not become 0
depending on the Iφ:Bφ clock
ratio. Tables 7.21 and 7.22
show the relationship between
the clock ratio and the
minimum number of internal
bus idle cycles.
[7] Write data wait During write access, a write cycle is 0 or 1
cycles
executed on the external bus only
after the write data becomes ready.
This write data wait period
generates idle cycles before the
write cycle. Note that when the
previous cycle is a write cycle and
the internal bus idle cycles are
shorter than the previous write
cycle, write data can be prepared in
parallel with the previous write cycle
and therefore, no idle cycle is
generated (write buffer effect).
For write → write or write →
read access cycles,
successive access cycles
without idle cycles are
frequently available due to the
write buffer effect described in
the left column. If successive
access cycles without idle
cycles are not allowed, specify
the minimum number of idle
cycles between access cycles
through CSnBCR.
[8] Idle cycles
To ensure the minimum pulse width 0 to 2.5 The number of idle cycles
between
on the signal-multiplexed pins, idle
depends on the target memory
different
cycles may be inserted before
types. See table 7.23.
memory types access after memory types are
switched. For some memory types,
idle cycles are inserted even when
memory types are not switched.
Rev. 1.00 Nov. 14, 2007 Page 286 of 1262
REJ09B0437-0100