SH7670 Datasheet, PDF (427/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Initial
Bit
Bit Name Value R/W
18
PFR
0
R/W
17
RXF
0
R/W
16
TXF
0
R/W
15 to 13 
All 0
R
12
PRCEF 0
R/W
11, 10 
All 0
R
9
MPDE 0
R/W
8, 7

All 0
R
Section 12 Ethernet Controller (EtherC)
Description
PAUSE Frame Receive Mode
0: PAUSE frame is not transferred to the E-DMAC
1: PAUSE frame is transferred to the E-DMAC
Receive Flow Control Operating Mode
0: PAUSE frame detection function is disabled
1: Receive flow control function is enabled
Transmit Flow Control Operating mode
0: Transmit flow control function is disabled
1: Transmit flow control function is enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
Permit Receive CRC Error Frame
0: A frame with a CRC error is received as a frame
with an error.
1: A frame with a CRC error is received as a frame
without an error.
For a frame with an error, a CRC error is reflected in
the ECSR of the E-DMAC and the status of the receive
descriptor. For a frame without an error, the frame is
received as normal frame.
Reserved
These bits are always read as 0. The write value
should always be 0.
Magic Packet Detection Enable
Enables or disables Magic Packet detection by
hardware to allow activation from the Ethernet.
0: Magic Packet detection is not enabled
1: Magic Packet detection is enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 14, 2007 Page 401 of 1262
REJ09B0437-0100