SH7670 Datasheet, PDF (1012/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Base clock
Receive data
(RxD)
Synchronization
sampling timing
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
–7.5 clocks
+7.5 clocks
Start bit
D0
D1
Data sampling
timing
Figure 22.19 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = { (0.5 − ¹ ) − (L − 0.5) F − ^{D − 0.5} (1 + F) } × 100 %
2N
N
Where: M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
M = (0.5 − 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 1.00 Nov. 14, 2007 Page 986 of 1262
REJ09B0437-0100