SH7670 Datasheet, PDF (783/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
17.3.40 Bus Wait Register (D0FWAIT, D1FWAIT)
D0FWAIT and D1FWAIT each specify the number of access waits for those registers of this
module that are connected to the internal bus (that is, D0FWAIT, D1FWAIT, D0FIFO, and
D1FIFO). The basic clock for this module is a USB clock of 48 MHz, and access from the internal
bus is performed through Bφ synchronization. For this reason, the USB clock must be multiplied
by a certain number of cycles when accessing registers of this module via the internal bus. The
number of access waits should be adjusted to produce at least the approximate value shown below:
83.4 ns (USB clock × 4 cycles) when the size of access is 32 bits, 41.7 ns (USB clock × 2 cycles)
when the size of access is 16 bits, or 20.8 ns (USB clock × 1 cycle) when the size of access is 8
bits.
Bit: 15 14 13 12 11 10
—
—
—
—
—
—
Initial Value: 0
0
0
0
0
0
R/W: R
R
R
R
R
R
Initial
Bit
Bit Name
Value R/W
15 to 4 
All 0
R
3 to 0 BWAIT[3:0] 1111 R/W
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
BWAIT[3:0]
0
0
0
0
0
0
1
1
1
1
R
R
R
R
R
R R/W R/W R/W R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Bus Wait between DMAC and FIFO
On a Bφ basis, set the number of waits needed when
accessing registers of this module via the internal
bus.
0000: 0 wait (accessing two cycles on a Bφ basis)
0001: 1 wait (accessing three cycles on a Bφ basis)
0010: 2 waits (accessing four cycles on a Bφ basis)
:
1111: 15 waits (accessing 17 cycles on a Bφ basis)
Note: Be sure to set this bit in the initialization
routine of this module by taking into account
the Bφ and access size.
Rev. 1.00 Nov. 14, 2007 Page 757 of 1262
REJ09B0437-0100