SH7670 Datasheet, PDF (41/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 1 Overview
Classification Symbol
Interrupts
NMI
IRQ7 to IRQ0
Address bus
Data bus
Bus control
A25 to A00
D31 to D00
CS0, CS3 to CS6
RD
RD/WR
BS
WE3
WE2
WE1
WE0
WAIT
RAS
CAS
CKE
DQMUU
I/O Name
Function
I Non-maskable
interrupt
Non-maskable interrupt request pin.
Fix it high when not in use.
I Interrupt requests Maskable interrupt request pins
7 to 0
Level-input or edge-input detection
can be selected. When the edge-input
detection is selected, the rising edge
or falling edge can also be selected.
O Address bus
Addresses are output on these pins.
I/O Data bus
Bidirectional data bus pins
O Chip select 0, 3 to Chip-select signal pins for external
6
memory or devices
O Read
Indicates that data is read from an
external device.
O Read/write
Read/write signal pin
O Bus start
Bus cycle start signal pin
O Most significant
byte write
Indicates that data is written to data
bits 31 to 24 of the external memory or
device.
O Second byte write Indicates that data is written to data
bits 23 to 16 of the external memory or
device.
O Third byte write
Indicates that data is written to data
bits 15 to 8 of the external memory or
device.
O Least significant Indicates that data is written to data
byte write
bits 7 to 0 of the external memory or
device.
I Wait
Input pin to insert a wait cycle into bus
cycles during access to the external
space
O RAS
Pin connected to the RAS pin of
SDRAM
O CAS
Pin connected to the CAS pin of
SDRAM
O Clock enable
Pin connected to the CKE pin of
SDRAM
O Most significant Selects data bus bits 31 to 24 of
byte select
SDRAM.
Rev. 1.00 Nov. 14, 2007 Page 15 of 1262
REJ09B0437-0100