SH7670 Datasheet, PDF (582/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
15.3.6 STIF Interrupt Enable Register (STIER)
STIER is a 32-bit register to control various interrupt requests. STIER is initialized to H'00000000
by a power-on reset.
Initial
Bit
Bit Name Value
31 to 13 
All 0
12
LKZE
0
11
LKE
0
10
DISE
0
9
UNZE
0
8
PCRE
0
7
TENDE 0
6
RENDE 0
5
RCVE3 0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Enables or disables LKZF interrupt requests.
0: LKZF interrupt requests are disabled.
1: LKZF interrupt requests are enabled.
Enables or disables LKF interrupt requests.
0: LKF interrupt requests are disabled.
1: LKF interrupt requests are enabled.
Enables or disables DISF interrupt requests.
0: DISF interrupt requests are disabled.
1: DISF interrupt requests are enabled.
Enables or disables UNZF interrupt requests.
0: UNZF interrupt requests are disabled.
1: UNZF interrupt requests are enabled.
Enables or disables PCRF interrupt requests.
0: PCRF interrupt requests are disabled.
1: PCRF interrupt requests are enabled.
Enables or disables TENDF interrupt requests.
0: TENDF interrupt requests are disabled.
1: TENDF interrupt requests are enabled.
Enables or disables RENDF interrupt requests.
0: RENDF interrupt requests are disabled.
1: RENDF interrupt requests are enabled.
Enables or disables RCVF3 interrupt requests.
0: RCVF3 interrupt requests are disabled.
1: RCVF3 interrupt requests are enabled.
Rev. 1.00 Nov. 14, 2007 Page 556 of 1262
REJ09B0437-0100