SH7670 Datasheet, PDF (614/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 16 Serial Sound Interface (SSI)
16.3 Register Description
The SSI has the following registers. Note that explanation in the text does not refer to the
channels.
Table 16.2 Register Description
Channel Register Name
Abbrevia-
tion
R/W Initial Value Address
Access
Size
0
Control register 0
SSICR_0 R/W H’00000000 H'FFFEC000 32
Status register 0
SSISR_0 R/W* H’02000003 H'FFFEC004 32
Transmit data register 0 SSITDR_0 R/W H’00000000 H'FFFEC008 32
Receive data register 0 SSIRDR_0 R H’00000000 H'FFFEC00C 32
1
Control register 1
SSICR_1 R/W H’00000000 H'FFFEC800 32
Status register 1
SSISR_1 R/W* H’02000003 H'FFFEC804 32
Transmit data register 1 SSITDR_1 R/W H’00000000 H'FFFEC808 32
Receive data register 1 SSIRDR_1 R H’00000000 H'FFFEC80C 32
0
SSI clock selection
SCSR_0 R/W H’0000
H'FFFF0000 16
register 0
1
SSI clock selection
SCSR_1 R/W H’0000
H'FFFF0800 16
register 1
Note: * Although bits 26 and 27 in this register can be read from or written to, bits other than
these are read-only. For details, refer to section 16.3.2, Status Register (SSISR).
Rev. 1.00 Nov. 14, 2007 Page 588 of 1262
REJ09B0437-0100