SH7670 Datasheet, PDF (521/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
ad_irqc0_n
ad_irqc1_n
A-DMAC
CPU control
CPU control data
ADMA interrupt
Channel 0 for checksum
Function
· DMA automatic
processing
· Checksum operation
· Processing data
management,
Data selector
Channel0 control
Channel0 data
Arbiter
Channel 1 for checksum
Function
Function
· Arbitration
Channel1 control
· DMA automatic
processing
· Checksum operation
· Processing data
management,
Data selector
Channel1 data
BUS I/F control
BUS I/F data
STIF0 I/F control
STIF0 I/F data
STIF1 I/F control
STIF1 I/F data
I-BUS
interface
Function
· Bus protocol
conversion
INTC
I-BUS control
I-BUS data
I-BUS
STIF0
interface
Function
· STIF0 protocol
conversion
STIF0control
STIF0 data ^STIF0
STIF1
interface
Function
· STIF1 protocol
conversion
STIF1 control
STIF1 data ^STIF1
ad_irqfec_n
x_rst
x_bck
x_bckstp_p
x_modstp_p
FEC channel
Function
· DMA autmatic
processing
· XOR operation
FEC
channel control
FEC
channel data
Figure 14.1 Block Diagram of A-DMAC
Rev. 1.00 Nov. 14, 2007 Page 495 of 1262
REJ09B0437-0100