SH7670 Datasheet, PDF (1121/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 28 List of Registers
Section 28 List of Registers
This section gives information on the on-chip I/O registers of this LSI as follows.
1. Register Addresses (by functional module, in order of the manual's section numbers):
• Registers are described by functional module, in order of the manual's section numbers.
• Access to reserved addresses that are not described in this list of register addresses is
prohibited.
• When addresses consist of 16 or 32 bits, the addresses of the MSBs are given on the
assumption that big-endian mode is selected.
2. Register Bits:
• Bit configurations of the registers are described in the same order as the list of register
addresses (by functional module, in order of the manual's section numbers).
• Reserved bits are indicated by "" in the bit name.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
3. Register States in Each Operating Mode:
• States of the registers are described in the same order as the list of register addresses (by
functional module, in order of the manual's section numbers).
• For the initial state of each bit, refer to the description of the register in the corresponding
section.
• The register states described are for basic operating modes. If there is a specific reset for an on-
chip peripheral module, refer to the section on that on-chip peripheral module.
4. Cautions Required when Writing into Registers in On-Chip Peripheral Modules:
Accessing a register in an on-chip peripheral module takes at least two cycles of the peripheral
module clock (Pφ) from the internal bus. When, meanwhile, writing from the CPU to an on-
chip peripheral module, the CPU executes subsequent instructions without waiting for the
register writing to be completed.
Here is an example involving a state transition to software standby mode for the purpose of
reducing power consumption. This transition requires a SLEEP instruction to be executed after
the SYBY bit of the STBCR register is set to 1. Before the execution of the SLEEP instruction,
actually, it is necessary to read the STBCR register on a dummy basis. In the absence of
dummy reading, the CPU executes the SLEEP instruction before the SYBY bit is set to 1, so
that the state occurring after the transition will be not software standby mode, but sleep mode.
Dummy-reading the STBCR register is thus required to wait until writing into the STBY bit is
completed.
Rev. 1.00 Nov. 14, 2007 Page 1095 of 1262
REJ09B0437-0100