SH7670 Datasheet, PDF (479/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)
TRSCER specifies whether or not transmit and receive status information reported by bits in the
EtherC/E-DMAC status register is to be indicated in bits TFS26 to TFS0 and RFS26 to RFS0 in
the corresponding descriptor. Bits in this register correspond to bits 11 to 0 in the EtherC/E-
DMAC status register (EESR). When a bit is cleared to 0, the transmit status (bits 11 to 8 in
EESR) is indicated in bits TFS3 to TFS0 in the transmit descriptor, and the receive status (bits 7 to
0 in EESR) is indicated in bits RFS7 to RFS0 of the receive descriptor. When a bit is set to 1, the
occurrence of the corresponding interrupt is not indicated in the descriptor. After this LSI is reset,
all bits are cleared to 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6




CNDCE DLCCE
CDCE
TROCE
RMAF
CE

Initial Value: 0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R/W R
5
4
3
2
1
0

RRFCE
RTLF
CE
RTSF
CE
PRECE
CERF
CE
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 12 
Initial
value
All 0
11
CNDCE 0
10
DLCCE
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W CND Bit Copy Directive
0: Indicates the CND bit state in bit TFS3 in the transmit
descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit TFS3 of the transmit descriptor
R/W DLC Bit Copy Directive
0: Indicates the DLC bit state in bit TFS2 of the transmit
descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit TFS2 of the transmit descriptor
Rev. 1.00 Nov. 14, 2007 Page 453 of 1262
REJ09B0437-0100