SH7670 Datasheet, PDF (695/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
4
SACKE
0
R/W Setup Transaction Normal Response Interrupt
Enable
Enables or disables the USB interrupt output when
the SACK interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
3 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: The INTENB1 register bits can be set to 1 only when the host controller function is selected;
do not set these bits to 1 to enable the corresponding interrupt output when the function
controller function is selected.
17.3.12 BRDY Interrupt Enable Register (BRDYENB)
BRDYENB is a register that enables or disables the BRDY bit in INTSTS0 to be set to 1 when the
BRDY interrupt is detected for each pipe.
On detecting the BRDY interrupt for the pipe corresponding to the bit in this register to which
software has set 1, this module sets 1 to the corresponding PIPEBRDY bit in BRDYSTS and the
BRDY bit in INTSTS0, and generates the BRDY interrupt.
While at least one PIPEBRDY bit in BRDYSTS indicates 1, this module generates the BRDY
interrupt when software modifies the corresponding interrupt enable bit in BRDYENB from 0 to
1.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0
BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 14, 2007 Page 669 of 1262
REJ09B0437-0100