SH7670 Datasheet, PDF (12/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

6.4.1 NMI Interrupt.................................................................................................... 143
6.4.2 User Break Interrupt ......................................................................................... 143
6.4.3 H-UDI Interrupt ................................................................................................ 143
6.4.4 IRQ Interrupts................................................................................................... 144
6.4.5 On-Chip Peripheral Module Interrupts ............................................................. 145
6.5 Interrupt Exception Handling Vector Table and Priority.................................................. 146
6.6 Operation .......................................................................................................................... 151
6.6.1 Interrupt Operation Sequence ........................................................................... 151
6.6.2 Stack after Interrupt Exception Handling ......................................................... 154
6.7 Interrupt Response Time................................................................................................... 155
6.8 Register Banks .................................................................................................................. 161
6.8.1 Banked Register and Input/Output of Banks .................................................... 162
6.8.2 Bank Save and Restore Operations................................................................... 162
6.8.3 Save and Restore Operations after Saving to All Banks................................... 164
6.8.4 Register Bank Exception .................................................................................. 165
6.8.5 Register Bank Error Exception Handling ......................................................... 165
6.9 Data Transfer with Interrupt Request Signals................................................................... 166
6.9.1 Handling Interrupt Request Signals as Sources for
CPU Interrupt but Not DMAC Activating ........................................................ 167
6.9.2 Handling Interrupt Request Signals as Sources for
Activating DMAC but Not CPU Interrupt ........................................................ 167
6.10 Usage Note ....................................................................................................................... 168
6.10.1 Timing to Clear an Interrupt Source ................................................................. 168
Section 7 Bus State Controller (BSC) ............................................................... 169
7.1 Features............................................................................................................................. 169
7.2 Input/Output Pins.............................................................................................................. 172
7.3 Area Overview.................................................................................................................. 174
7.3.1 Address Map..................................................................................................... 174
7.3.2 Data Bus Width and Pin Function Setting in Each Area .................................. 175
7.4 Register Descriptions........................................................................................................ 176
7.4.1 Common Control Register (CMNCR) .............................................................. 177
7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 3 to 6) ............................. 179
7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3 to 6) .......................... 184
7.4.4 SDRAM Control Register (SDCR)................................................................... 205
7.4.5 Refresh Timer Control/Status Register (RTCSR)............................................. 208
7.4.6 Refresh Timer Counter (RTCNT)..................................................................... 210
7.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 211
7.4.8 AC Characteristics Switching Register (ACSWR) ........................................... 212
7.4.9 AC Characteristics Switching Key Register (ACKEYR) ................................. 213
Rev. 1.00 Nov. 14, 2007 Page xii of xxvi