SH7670 Datasheet, PDF (76/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 2 CPU
Operation
Classification Types Code
Function
Arithmetic
26
operations
ADD
ADDC
Binary addition
Binary addition with carry
ADDV
Binary addition with overflow check
CMP/cond Comparison
CLIPS
Signed saturation value comparison
CLIPU
Unsigned saturation value comparison
DIVS
Signed division (32 ÷ 32)
DIVU
Unsigned division (32 ÷ 32)
DIV1
One-step division
DIV0S
Initialization of signed one-step division
DIV0U
Initialization of unsigned one-step division
DMULS Signed double-precision multiplication
DMULU Unsigned double-precision multiplication
DT
Decrement and test
EXTS
Sign extension
EXTU
Zero extension
MAC
Multiply-and-accumulate, double-precision
multiply-and-accumulate operation
MUL
Double-precision multiply operation
MULR
Signed multiplication with result storage in Rn
MULS
Signed multiplication
MULU
Unsigned multiplication
NEG
Negation
NEGC
Negation with borrow
SUB
Binary subtraction
SUBC
Binary subtraction with borrow
SUBV
Binary subtraction with underflow
No. of
Instructions
40
Rev. 1.00 Nov. 14, 2007 Page 50 of 1262
REJ09B0437-0100