SH7670 Datasheet, PDF (486/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name value R/W Description
1
EDH
0
R/W E-DMAC Halted
0: The E-DMAC is operating normally
1: The E-DMAC has been halted by NMI pin assertion.
E-DMAC operation is restarted by writing 0
0

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
13.2.14 Receiving-Buffer Write Address Register (RBWAR)
RBWAR stores the address of data to be written in the receiving buffer when the E-DMAC writes
data to the receiving buffer. Which addresses in the receiving buffer are processed by the E-
DMAC can be recognized by monitoring addresses displayed in this register. The address that the
E-DMAC is actually processing may be different from the value read from this register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RBWA[31:16]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RBWA[15:0]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name value R/W Description
31 to 0 RBWA[31:0] All 0
R
Receiving-Buffer Write Address
These bits can only be read. Writing is prohibited.
Rev. 1.00 Nov. 14, 2007 Page 460 of 1262
REJ09B0437-0100